In a multiprocessor system, each processor has a one-level or two-level cache (cache). Multiple duplicates of one piece of data may simultaneously exist in different caches. If a processor freely modifies a local duplicate, results observed by different processors may be inconsistent. In addition, modification performed by an Input Output (IO) on a main memory may also cause an inconsistency problem. To solve the problem of cache consistency, the Modified Exclusive Shared Invalid (MESI) protocol is introduced. A cache includes multiple cache lines. The MESI protocol specifies that, data in each cache line has four states: an M (Modified) state, an E (Exclusive) state, an S (Shared) state, and an I (Invalid) state, where the M state refers to that the cache line is modified and only exists in the cache; the E state refers to that the cache line is the same as the main memory and only exists in the cache; the S state refers to that the cache line is the same as the main memory and also possibly exists in another cache; and the I state refers to that the cache line is invalid and there is no such data in the cache.
Generally, a main memory of a computer system requests to access in a unit of a cache line. Current directory design provides a directory entry for each cache line to record information indicating that a remote node occupies the cache line. A cache consistency protocol of a current computer system is generally a consistency protocol based on a directory. An inclusive policy is used between the main memory and the cache, and when storage space of the main memory is insufficient, replacement needs to be performed. Invalid listening is performed on an original directory item, and then the item is written back or discarded. For M-state data, because a unique duplicate of a whole system is in the cache, when the M-state data is replaced, a write-back command is generated to write the data into the cache; however, E-state data or S-state data has not been modified in the cache, and a same duplicate also exists in the main memory; if the E-state data or the S-state data is replaced, the data is discarded according to a protocol requirement or a removal command is generated, and space is vacated to store data required by a new request.
Currently, quite a few systems use a policy of directly discarding the data, causing that directory information of a main memory is inaccurate. After the directory of the main memory is full, replacement is also caused. No matter whichever replacement policy is used, data that is being used by the cache is possibly replaced, thereby affecting performance of a whole system.
Storage space of the directory of the main memory is limited, and only data which has existed in the cache is stored in the storage space. Because directory information of the main memory is inaccurate, the main memory stores some invalid content in the cache, thereby leading to a space waste of the directory of the main memory. When the storage space is insufficient, replacement may occur. No matter whichever replacement algorithm is used, it is always possible that a replaced cache line is data being used in a processor, and when the data is replaced, normal working of the processor is interrupted, and therefore system performance is affected.